1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a logic device using multi-step sidewall spacer formation.
2. Description of the Prior Art
For logic devices of modern integrated circuits, the narrow line effect of the titanium-salicide technology becomes a bottleneck while the dimension of the devices has been rapidly decreasing. In order to overcome this problem, as shown in FIGS. 1A and 1B, an over etch process of the sidewall spacer 180A around the gate (160, 140, and 120) is usually applied, so that the top surface of the sidewall spacer 180A is over etched (about 500 angstroms) below the top surface of the gate. Unfortunately, the width of the sidewall spacer 180A is also accordingly reduced, resulting a sidewall spacer too narrow for the purpose of isolation.
In the prior art, in order to solve the aforementioned dilemma, a thicker spacer (e.g. 1500-2000 angstroms compared to conventional 1000 angstroms) is used, which results in a sidewall spacer with enough width for isolation. However, this solution is not feasible for fabricating devices with dimension below 0.18 micrometer due to lack of space between gates. Further, width of the lightly doped drain (LDD) increases accordingly, which causes high resistivity and low speed for the devices. Furthermore, this solution causes top gate polysilicon (TGP) corner loss owing to heavy Ar bombardment during long spacer etch.
For the foregoing reasons, there is a need for a method of forming a logic device in the integrated circuits whose sidewall spacer has enough width for isolation without aforementioned disadvantages.